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SLE24C164-S Fiches technique(PDF) 9 Page - Siemens Semiconductor Group

No de pièce SLE24C164-S
Description  16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
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Fabricant  SIEMENS [Siemens Semiconductor Group]
Site Internet  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

SLE24C164-S Fiches technique(HTML) 9 Page - Siemens Semiconductor Group

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SLx 24C164
Semiconductor Group
9
1998-07-27
4
Device Addressing and EEPROM Addressing
After a START condition, the master always transmits a Command Byte CSW or CSR.
After the acknowledge of the EEPROM a Control Byte follows, its content and the
transmitter depend on the previous Command Byte. The description of the Command
and Control Bytes is shown in table 2.
The device has an internal address counter which points to the current EEPROM
address.
The address counter is incremented
– after a data byte to be written has been acknowledged, during entry of further data
byte
– during a byte read, thus the address counter points to the following address after
reading a data byte.
Command Byte
Selects one of the 8 addressable devices: the chip select bits c2,
c1 and c0 (bit positions b6 to b4) are compared to their
corresponding hard wired input pins CS2, CS1 and CS0,
respectively (c1 is the complement of CS1 pin).
Selects operation: the least significant bit b0 is low for a write
operation (Chip Select Write Command Byte CSW) or set high for a
read operation (Chip Select Read Command Byte CSR).
Contains address information: in the CSW Command Byte, the
bit positions b3 to b1 are decoded for the three uppermost EEPROM
address bits A10, A9, A8 (in the CSR Command Byte, the bit
positions b3 to b1 are left undefined).
Control Byte
Following CSW (b0 = 0): contains the eight lower bits of the
EEPROM address (EEA) bit A7 to A0.
Following CSR (b0 = 1): contains the data read out, transmitted by
the EEPROM. The EEPROM data are read as long as the master
pulls down SDA after each byte in order to acknowledge the
transfer. The read operation is stopped by the master by releasing
SDA (no acknowledge is applied) followed by a STOP condition.
Table 2
Command and Control Byte for I
2C-Bus Addressing of Chip and EEPROM
Definition
Function
b7
b6
b5
b4
b3
b2
b1
b0
CSW
1
c2
c1
c0
A10 A9A80
Chip Select for Write
CSR
1
c2
c1
c0
x
x
x
1
Chip Select for Read
EEA
A7 A6 A5 A4 A3
A2 A1 A0 EEPROM address


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