ADV3205-EVALZ datasheet(9/20 Pages) AD

No de pièce	ADV3205-EVALZ

Description	60 MHz, G = 2, 16 횞 16

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Fabricant	AD [Analog Devices]

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Data Sheet

ADV3205

Rev. 0 | Page 9 of 20

TRUTH TABLE AND LOGIC DIAGRAM

Table 8. Operation Truth Table1

CE

UPDATE

CLK

DATA IN

DATA OUT

RESET

SER/PAR

Operation/Comment

1

X

No change in logic.

0

1

↓2

Data i

Data i-80

1

0

The data on the serial DATA IN line is loaded into the serial

register. The first bit clocked into the serial register appears at

DATA OUT 80 clocks later.

0

1

↓3

D0 ... D4,

A0 ... A3

Not

applicable

in parallel

mode

1

The data on the parallel data lines, D0 to D4, are loaded into

the 80-bit serial shift register location addressed by A0 to A3.

0

X

1

X

Data in the 80-bit shift register transfers into the parallel

latches that control the switch array. Latches are transparent.

X

0

X

Asynchronous operation. All outputs are disabled. Remainder

of logic is unchanged.

1 X = don’t care, 0 = logic low, 1 = logic high, and

↓ = falling edge triggered.

2

↓ = falling edge triggered.

3

↓ = low level triggered.

D

CLK

Q

A0

A1

A2

CLK

16

256

DATA IN

(SERIAL)

(OUTPUT

ENABLE)

SER/PAR

CE

UPDATE

OUT00 EN

DATA

OUT

PARALLEL

DATA

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLK

D1

D2

D3

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLK

OUT01 EN

OUT02 EN

OUT03 EN

OUT04 EN

OUT05 EN

OUT06 EN

OUT07 EN

D

LE

Q

CLR

OUT15

EN

OUTPUT ENABLE

SWITCH MATRIX

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

S

D1

Q

D0

D Q

CLK

S

D1

Q

D0

D4

DECODE

D

LE

Q

CLR

OUT00

EN

D

LE

OUT00

B0

Q

D

LE

Q

OUT00

B1

D

LE

Q

OUT00

B2

D

LE

Q

OUT00

B3

D

LE

OUT01

B0

Q

D

LE

Q

CLR

OUT14

EN

D

LE

OUT15

B0

Q

D

LE

OUT15

B1

Q

D

LE

OUT15

B2

Q

D Q

CLK

S

D1

Q

D0

S

D1

Q

D0

D

LE

OUT15

B3

Q

S

D1

Q

D0

OUT08 EN

OUT09 EN

OUT10 EN

OUT11 EN

OUT12 EN

OUT13 EN

OUT14 EN

OUT15 EN

A3

RESET

(OUTPUT ENABLE)

Figure 6. Logic Diagram

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