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SAB80C517A Fiches technique(PDF) 67 Page - Siemens Semiconductor Group |
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SAB80C517A Fiches technique(HTML) 67 Page - Siemens Semiconductor Group |
67 / 77 page SAB 80C517A/83C517A-5 Semiconductor Group 66 1994-05-01 AC Characteristics (cont’d) Parameter Symbol Limit Values Unit 18 MHz Clock Variable Clock 1/t CLCL = 3.5 MHz to 18 MHz min. max. min. max. External Data Memory Characteristics RD pulse width tRLRH 233 – 6 tCLCL – 100 – ns WR pulse width tWLWH 233 – 6 tCLCL – 100 – ns Address hold after ALE tLLAX2 81 – 2 tCLCL – 30 – ns RD to valid data in tRLDV – 128 – 5 tCLCL – 150 ns Data hold after RD tRHDX 0 – 0–ns Data float after RD tRHDZ –51 – 2 tCLCL – 60 ns ALE to valid data in tLLDV – 294 – 8 tCLCL – 150 ns Address to valid data in tAVDV – 335 – 9 tCLCL – 165 ns ALE to WR or RD tLLWL 117 217 3 tCLCL – 50 3 tCLCL +50 ns WR or RD high to ALE high tWHLH 16 96 tCLCL – 40 tCLCL +40 ns Address valid to WR tAVWL 92 – 4 tCLCL – 130 – ns Data valid to WR transition tQVWX 11 – tCLCL – 45 – ns Data setup before WR tQVWH 239 – 7 tCLCL – 150 – ns Data hold after WR tWHQX 16 – tCLCL – 40 – ns Address float after RD tRLAZ – 0 –0ns |
Numéro de pièce similaire - SAB80C517A |
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Description similaire - SAB80C517A |
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