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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TSL2571 Fiches technique(PDF) 5 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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TSL2571 Fiches technique(HTML) 5 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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5 / 24 page  TSL2571 LIGHT-TO-DIGITAL CONVERTER TAOS117A − FEBRUARY 2011 5 The LUMENOLOGY r Company r r Copyright E 2011, TAOS Inc. www.taosinc.com Wait Characteristics, VDD = 3 V, TA = 255C, WEN = 1 (unless otherwise noted) PARAMETER TEST CONDITIONS CHANNEL MIN TYP MAX UNIT Wait step size WTIME = 0xFF 2.58 2.72 2.9 ms Wait number of integration steps 1 256 steps AC Electrical Characteristics, VDD = 3 V, TA = 255C (unless otherwise noted) PARAMETER† TEST CONDITIONS MIN TYP MAX UNIT f(SCL) Clock frequency (I2C only) 0 400 kHz t(BUF) Bus free time between start and stop condition 1.3 μs t(HDSTA) Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 μs t(SUSTA) Repeated start condition setup time 0.6 μs t(SUSTO) Stop condition setup time 0.6 μs t(HDDAT) Data hold time 0 μs t(SUDAT) Data setup time 100 ns t(LOW) SCL clock low period 1.3 μs t(HIGH) SCL clock high period 0.6 μs tF Clock/data fall time 300 ns tR Clock/data rise time 300 ns Ci Input pin capacitance 10 pF † Specified by design and characterization; not production tested. PARAMETER MEASUREMENT INFORMATION SDA SCL Stop Start SCLACK t(LOWMEXT) t(LOWMEXT) t(LOWSEXT) SCLACK t(LOWMEXT) Start Condition Stop Condition P SDA t(SUSTO) t(SUDAT) t(HDDAT) t(BUF) VIH VIL SCL t(SUSTA) t(HIGH) t(F) t(R) t(HDSTA) t(LOW) VIH VIL PS S Figure 1. Timing Diagrams |
Numéro de pièce similaire - TSL2571 |
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Description similaire - TSL2571 |
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