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74AUP2G125GM Fiches technique(PDF) 3 Page - NXP Semiconductors |
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74AUP2G125GM Fiches technique(HTML) 3 Page - NXP Semiconductors |
3 / 24 page 74AUP2G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 — 2 December 2011 3 of 24 NXP Semiconductors 74AUP2G125 Low-power dual buffer/line driver; 3-state 6. Pinning information 6.1 Pinning Fig 3. Logic diagram (one gate) mna227 nOE nA nY Fig 4. Pin configuration SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74AUP2G125 1OE VCC 1A 2OE 2Y 1Y GND 2A 001aae973 1 2 3 4 6 5 8 7 74AUP2G125 1Y 2OE VCC 2A 2Y 1A 1OE GND 001aae974 36 27 18 45 Transparent top view Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-1 001aaj471 74AUP2G125 Transparent top view 8 7 6 5 1 2 3 4 1OE 1A 2Y GND VCC 2OE 1Y 2A 001aae975 1A 1Y 1OE 2Y 2OE 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74AUP2G125 |
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