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MC88LV926 Fiches technique(PDF) 4 Page - Motorola, Inc |
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MC88LV926 Fiches technique(HTML) 4 Page - Motorola, Inc |
4 / 10 page MC88LV926 MOTOROLA TIMING SOLUTIONS BR1333 — REV 5 4 Figure 1. MC88LV926 Logic Block Diagram VCO CH PUMP PFD SYNC1 PLL_EN MR POWER–ON RESET 01 LOCK INDICATOR RESET_OUT RST_IN RST_OUT 2X_Q ÷8 ÷2 R Q0 ÷4 R Q1 ÷4 R Q2 ÷4 R Q3 ÷4 R CLKEN ÷4 R DELAY Q Q Q Q Q SYNC INPUT TIMING REQUIREMENTS Symbol Parameter Minimum Maximum Unit tRISE/FALL SYNC Input Rise/Fall Time, SYNC Input From 0.8V to 2.0V — 5.0 ns tCYCLE, SYNC Input Input Clock Period SYNC Input 1 f2X_Q 4 200 ns Duty Cycle Duty Cycle, SYNC Input 50% ± 25% FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V or 5.0V ±5%) Symbol Parameter Guaranteed Minimum Unit Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 66 MHz Fmax (‘Q’) Maximum Operating Frequency, Q0–Q3 Outputs 33 MHz Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition. |
Numéro de pièce similaire - MC88LV926 |
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Description similaire - MC88LV926 |
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