SIC413DB datasheet(9/18 Pages) VISHAY

No de pièce	SIC413DB

Description	microBUCK SiC413 4-A, 26-V Integrated Synchronous Buck Regulator

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Vishay Siliconix

SiC413

Document Number: 69057

S09-2250-Rev. D, 26-Oct-09

www.vishay.com

9

APPLICATION NOTES

Inductor Selection

The inductor is one of the energy storage components in

a converter. Choosing an inductor means specifying its

size, structure, material, inductance, saturation level,

DC-resistance (DCR), and core loss. Fortunately, there are

many inductor vendors that offer wide selections with ample

specifications and test data, such as Vishay Dale.

The following are some key parameters that users should

focus on. In PWM mode, inductance has a direct impact on

the ripple current. Assuming 100 % efficiency, the steady

state peak-to-peak inductor (L) ripple current (IPP) can be

calculated as

where f = switching frequency.

Higher inductance means lower ripple current, lower rms

current, lower voltage ripple on both input and output, and

higher efficiency, unless the resistive loss of the inductor

dominates the overall conduction loss. However, higher

inductance also means a bigger inductor size and a slower

response to transients. For fixed line and load conditions,

higher inductance results in a lower peak current for each

pulse, a lower load capability, and a higher switching

frequency. The saturation level is another important

parameter in choosing inductors. Note that the saturation

levels specified in data sheets are maximum currents. For a

dc-to-dc converter operating in PWM mode, it is the

maximum peak inductor (IPK) current that is relevant, and

can be calculated using these equations:

where IO = output current.

This peak current varies with inductance tolerance and other

errors,

and

the

rated

saturation

level

varies

over

temperature. So a sufficient design margin is required when

choosing current ratings. A high-frequency core material,

such as ferrite, should be chosen, the core loss could lead to

serious efficiency penalties. The DCR should be kept as low

as possible to reduce conduction losses.

Input Capacitor Selection

To minimize input voltage ripple caused by the step-down

conversion, and interference of large voltage spikes from

other circuits, a low-ESR input capacitor is required to filter

the input voltage. The input capacitor should be rated for the

maximum RMS input current of:

It is common practice to rate for the worst-case RMS ripple

that occurs when the duty cycle is at 50 %:

Output Capacitor Selection

The output capacitor affects output voltage ripple due to

2 reasons: the capacitance and the effective series

resistance (ESR). The selection of the output capacitor is

primarily determined by the capacitor ESR required

minimizing voltage ripple and current ripple. The relationship

between output ripple

ΔV

O, capacitance CO and its ESR is:

Multiple capacitors placed in parallel may be needed to meet

the ESR requirements. However if the ESR is too low it may

cause stability problems.

Control Loop Design

The SiC413CB is an integrated voltage mode buck

converter. The loop stability depends on input and output

voltage, output LC filter, the equivalent lumped capacitance,

resistance and inductance attached to the output voltage rail

beyond the LC filter. The output LC filter creates a two pole

roll-off of the loop gain that makes the closed loop system

inherently unstable. Therefore, a compensation network of

poles

and

zeros

must

be

implemented

to

achieve

unconditional stability.

Figure 4 shows a simplified diagram of the SiC413CB buck

converter control loop and the external elements that affect

loop gain, phase shift and stability. In this diagram L1, C4

and C5 and R6 form a first order model of low pass filter.

Resistor R6 represents the effective series resistance (ESR)

of C5, which is often the case of a polymer (tantalum)

capacitor. Ceramic (MLCC) capacitors are also used as

denoted by C4, which has near zero ESR. To balance the

performance and cost, the recommended output capacitor

configuration is a combination of low cost, high capacitance

polymer capacitors (C5) with ESR (R6) to add a zero to help

boost phase margin and MLCC capacitors (C4) that have low

ESR for achieving low voltage ripple. In practice, the lumped

equivalent capacitance at the output of the filter may be a

combination of many different kinds of capacitors. The

characteristics of these capacitors must be considered when

deriving the open loop transfer function and designing the

loop compensation. It is important to have a good

approximation

of

the

lumped

impedance

(capacitors,

resistors, ferrite beads,

π filters, etc.) tied to the rail before

calculating compensation network component values.

Resistor R1 and R2 form the feedback voltage divider that

samples the DC output and applies a feedback signal to the

FB pin.

Components C1, C2, C3, R4, R5 and the

transconductance

error

amplifier

form

the

loop

compensation network. With voltage mode control loop the

()

f

L

V

I

IN

O

IN

O

PP

.

-

.

=

2

PP

O

PK

I

I+

=

)

( -

=

IN

O

IN

O

MAX

O.

RMS

V

I

I1

2

.MAX.

O

RMS

I

I=

)

(

.

+

.

=

Δ

O

PP

O

C

f

ESR

I

V

8

1

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