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SI8902EDB Fiches technique(PDF) 5 Page - Vishay Siliconix |
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SI8902EDB Fiches technique(HTML) 5 Page - Vishay Siliconix |
5 / 9 page Document Number: 71862 S-83049-Rev. I, 22-Dec-08 www.vishay.com 5 Vishay Siliconix Si8902EDB PACKAGE OUTLINE MICRO FOOT: 6 BUMP (2 x 3, 0.8 mm PITCH) Notes (Unless Otherwise Specified): 1. 6 solder bumps are 95.5/3.8/0.7 Sn/Ag/Cu. 2. Backside surface is coated with a Ag/Ni/Ti layer. 3. Non-solder mask defined copper landing pad. 4. Laser marks on the silicon die back. Notes: a. Use millimeters as the primary measurement. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71862. Recommended Land Mark on Backside of Die e e 6 x 0.30 0.31 Note 3 Solder Mask - 0.4 8902E XXX D E s e e s Bump Note 1 A A2 A1 e Note 2 b Diameter e Dim. Millimetersa Inches Min. Max. Min. Max. A 0.600 0.650 0.0236 0.0256 A1 0.260 0.290 0.102 0.114 A2 0.33 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 D 1.520 1.600 0.0598 0.0630 E 2.320 2.400 0.0913 0.0945 e 0.750 0.850 0.0295 0.0335 s 0.380 0.400 0.0150 0.0157 |
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