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TPL0401B-10DCKR Fiches technique(PDF) 6 Page - Texas Instruments |
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TPL0401B-10DCKR Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 18 page TPL0401A TPL0401B SLIS144 – SEPTEMBER 2011 www.ti.com OPERATING SPECIFICATIONS Typical values are specified at 25 oC and Vdd=3.3V(1) CONDITION PARAMETER MIN TYP MAX UNIT S -40 to 85oC 0.5 uA IDD(STBY) VDD Standby current -40 to 125oC 1.5 uA IIN-DIG Digital Pins Leakage Current (SCL, SDA Inputs) -1 1 uA SERIAL INTERFACE SPECS (SDA, SCL) VIH Input high voltage 0.7 x VDD 5.5 V VIL Input low voltage 0 0.3 x VDD V SDA Pin, VOL Output low voltage 0.4 V IOL = 4 mA SCL, CIN Pin capacitance 7 pF SDA Inputs I2C INTERFACE TIMING REQUIREMENTS STANDARD MODE I2C FAST MODE I2C BUS UNITS BUS MIN MAX MIN MAX fSCL I2C Clock frequency 0 100 0 400 kHz tSCH I2C Clock high time 4 0.6 µs tSCL I2C Clock low time 4.7 1.3 µs tsp I2C Spike time 0 50 0 50 ns tSDS I2C Serial data setup time 250 100 ns tSDH I2C Serial data hold time 0 0 ns tICR I2C Input rise time 1000 20 + 0.1Cb 300 ns tICF I2C Input fall time 300 20 + 0.1Cb 300 ns tICF I2C Output fall time, 10 pF to 400 pF bus 300 20 + 0.1Cb 300 ns tBUF I2C Bus free time between stop and start 4.7 1.3 µs tSTS I2C Start or repeater start condition setup time 4.7 1.3 µs tSTH I2C Start or repeater start condition hold time 4 0.6 µs tSPS I2C Stop condition setup time 4 0.6 µs tVD(DATA) Valid data time, SCL low to SDA output valid 1 1 µs Valid data time of ACK condition, ACK signal from SCL low tVD(DATA) 1 1 µs to SDA (out) low (1) Parameters with Min and Max limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0401A TPL0401B |
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