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CBC012 Fiches technique(PDF) 3 Page - Cymbet Corporation |
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CBC012 Fiches technique(HTML) 3 Page - Cymbet Corporation |
3 / 5 page EnerChip™ CBC012 Solid State Energy Storage ©2009-2010Cymbet Corporation • Tel: +1-763-633-1780 • www.cymbet.com DS-72-02 Rev A Page 3 of 5 Package Dimensions - 6-pin DFN (package code D5) Pin Number(s) Description 1 V- 2,3,4,5 NIC 6 V+ Note: NIC = No Internal Connection Notes: 1. All linear dimensions are in millimeters. 2. Drawing is subject to change without notice. Printed Circuit Board (PCB) Layout Guidelines and Recommendations Electrical resistance of solder flux residue on PCBs can be low enough to partially or fully discharge the backup energy cell and in some cases can be comparable to the load typically imposed on the cell when delivering power to an integrated circuit in low power mode. Therefore, solder flux must be thoroughly washed from the board following soldering. The PCB layout can make this problem worse if the cell’s positive and negative terminals are routed near each other and under the package, where it is difficult to wash the flux residue away. An undesirable example is shown in Figure 1. The negative connection on the EnerChip is routed from the negative pad to a via placed under the package near the positive pad. In this scenario, solder flux residue can wick from the positive solder pad, covering both the positive pad and the via. This results in a high resistance current path between the EnerChip terminals. This current path will make the cell appear to be defective or make the application circuit appear to be drawing too much current. To avoid this situation, make sure positive and negative traces are routed outside of the package footprint, as shown in Figure 2, to ensure that flux residue will not cause a discharge path between the positive and negative pads. Similarly, a leakage current path can exist from the package lead solder pads to the exposed die pad on the underside of the package as well as any solder pad on the PCB that would be connected to that exposed die pad during the reflow solder process. Therefore, it is strongly recommended that the PCB layout not include a solder pad in the region where the exposed die pad of the package will land. It is sufficient to place PCB solder pads only where the package leads will be. That region of the PCB where the exposed die pad will land must not have any solder pads, traces, or vias. |
Numéro de pièce similaire - CBC012 |
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Description similaire - CBC012 |
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