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GS9060-CFE3 Fiches technique(PDF) 7 Page - Gennum Corporation

No de pièce GS9060-CFE3
Description  HD-LINX II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver
Download  61 Pages
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Fabricant  GENNUM [Gennum Corporation]
Site Internet  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9060-CFE3 Fiches technique(HTML) 7 Page - Gennum Corporation

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GS9060 Data Sheet
22208 - 8
January 2007
7 of 61
13
IOPROC_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the
device are enabled:
• EDH CRC Error Correction
• ANC Data Checksum Correction
• TRS Error Correction
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS
HIGH and disable the individual feature(s) in the
IOPROC_DISABLE register accesible via the host interface.
When set LOW, the I/O processing features of the device are
disabled, regardless of whether the features are enabled in the
IOPROC_DISABLE register.
14
CD2
Non
Synchronous
Input
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal.
Normally generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI2
and DDI2 pins is considered valid.
When HIGH, the associated serial digital input signal is
considered to be invalid. In this case, the LOCKED signal is set
LOW and all parallel outputs are muted.
15,17
DDI_2, DDI_2
Analog
Input
Differential input pair for serial digital input 2.
16
TERM2
Analog
Input
Termination for serial digital input 2. AC couple to
PDBUFF_GND.
18
SMPTE_BYPASS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device
will be configured to operate in SMPTE mode. All I/O processing
features may be enabled in this mode.
When set LOW, the device will not support the descrambling,
decoding or word alignment of received SMPTE data. No I/O
processing features will be available.
19
RSET
Analog
Input
Used to set the serial digital loop-through output signal
amplitude. Connect to CD_VDD through 281
Ω +/- 1% for
800mVp-p single-ended output swing.
20
CD_VDD
Power
Power supply connection for the serial digital cable driver.
Connect to +1.8V DC analog.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description


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