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TPS40400_1110 Fiches technique(PDF) 9 Page - Texas Instruments |
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TPS40400_1110 Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 72 page TPS40400 www.ti.com SLUS930B – APRIL 2011 – REVISED OCTOBER 2011 PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. Signal ground for the controller. Connect the ground of signal level circuits to this pin. Connections should be SGND PAD - arranged so that power level currents do not flow in the pad attached to the thermal plane or in the SGND portion of the circuit. SMBALRT 23 O Output used to signal that PMBus host that the controller needs attention. This is the common connection for the flying high-side FET driver and also serve as a sense line for the adaptive SW 17 I anti-cross-conduction circuitry Logic level input to the oscillator inside the controller. The oscillator resets on the rising edge of a pulse train SYNC 4 I applied to this pin and begin a new switching cycle. Analog input to the non inverting side of the control loop error amplifier. The error amplifier has three inputs (voltage reference, TRACK and soft-start ramp) to it ’s “+” side, and the lowest voltage applied to these three TRACK 5 I inputs dominate and control the output voltage of the whole converter. This pin is to allow the user to configure a voltage divider that allows the controller output follow an external reference voltage during startup. VDD 20 I Input power connection for the device. 3.0 V to 20 V required. VSNS+ 9 I Non-inverting input to the unity gain remote voltage sense amplifier. VSNS – 10 I Inverting input to the unity gain remote voltage sense amplifier. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :TPS40400 |
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