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GS1531 Fiches technique(PDF) 8 Page - Gennum Corporation |
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GS1531 Fiches technique(HTML) 8 Page - Gennum Corporation |
8 / 50 page GS1531 Data Sheet 30573 - 7 February 2008 8 of 50 B8, F8, J8 IO_GND – Power Ground connection for digital I/O buffers. Connect to digital GND. C2 PD_VDD – Power Power supply connection for the phase detector. Connect to +1.8V DC analog. C3 PD_GND – Power Ground connection for the phase detector. Connect to analog GND. D5 DVB_ASI Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode. When set LOW, the device will not support the encoding of received DVB-ASI data. D6 LOCKED Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. The LOCKED signal will be HIGH whenever the device has correctly received and locked to SMPTE compliant data in SMPTE mode or DVB-ASI compliant data in DVB-ASI mode, or when the device has achieved lock in Data-Through mode. It will be LOW otherwise. E4 SD/HD Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set LOW, the device will be configured to transmit signal rates of 1.485Gb/s or 1.485/1.001Gb/s only. When set HIGH, the device will be configured to transmit signal rates of 270Mb/s only. E5, F5 CORE_GND – Power Ground connection for the digital core logic. Connect to digital GND. E6, F6 CORE_VDD – Power Power supply connection for the digital core logic. Connect to +1.8V DC digital. F1 RSV – – Connect to Analog GND. F4 20bit/10bit Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the input data bus width in SMPTE or Data-Through modes. When set HIGH, the parallel input will be 20-bit demultiplexed data. When set LOW, the parallel input will be 10-bit multiplexed data. Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description |
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