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DAC1008D650_1012 Fiches technique(PDF) 4 Page - NXP Semiconductors |
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DAC1008D650_1012 Fiches technique(HTML) 4 Page - NXP Semiconductors |
4 / 98 page DAC1008D650 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 17 December 2010 4 of 98 NXP Semiconductors DAC1008D650 2 ×, 4× or 8× interpolating DAC with JESD204A 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 2. Pin configuration 005aaa155 DAC1008D650HN Transparent top view AGND VDDA(3V3) AGND VDDA(3V3) AUXBP AUXAP AUXBN AUXAN AGND AGND VDDA(1V8) VDDA(1V8) VDDA(1V8) VDDA(1V8) GAPOUT AGND VIRES CLKINP n.c. CLKINN RESET_N AGND SCS_N VDDA(1V8) VDDD(1V8) MDS_P SCLK MDS_N SDIO VDDD(1V8) SDO n.c. 16 33 15 34 14 35 13 36 12 37 11 38 10 39 9 40 8 41 7 42 6 43 5 44 4 45 3 46 2 47 1 48 terminal 1 index area Table 2. Pin description Symbol Pin Type[1] Description SDO 1 O SPI data output SDIO 2 I/O SPI data input/output SCLK 3 I SPI clock VDDD(1V8) 4 P digital supply voltage 1.8 V SCS_N 5 I SPI chip select (active LOW) RESET_N 6 I general reset (active LOW) n.c. 7 - not connected VIRES 8 I/O DAC biasing resistor GAPOUT 9 I/O bandgap input/output voltage VDDA(1V8) 10 P analog supply voltage 1.8 V VDDA(1V8) 11 P analog supply voltage 1.8 V |
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