Moteur de recherche de fiches techniques de composants électroniques |
|
ISL45042 Fiches technique(PDF) 5 Page - Intersil Corporation |
|
ISL45042 Fiches technique(HTML) 5 Page - Intersil Corporation |
5 / 9 page 5 FN6072.9 April 13, 2011 Application Information The application circuit to adjust the VCOM voltage in an LCD panel is shown in Figure 1. The ISL45042 has a 128-step sink current resolution. The output is connected to an external voltage divider that decreases the output VCOM voltage as you increase the ISL45042 sink current. CTL Pin The adjustment of the output VCOM voltage and the programming of the non-volatile memory are provided through a single pin called CTL when the CE pin is high. The output VCOM voltage is increased with a mid (VDD/2) to high transition (0.8*VDD) on the CTL pin. The output VCOM voltage is decreased with a mid (VDD/2) to low transition (0.3*VDD) on the CTL pin (see Figure 8). Once the minimum or maximum value is reached on the 128 steps, the device will not overflow or underflow beyond that minimum or maximum value. Programming of the non-volatile memory occurs when the CTL pin exceeds 4.9V. The CTL signal needs to remain above 4.9V for more than 200µs. The level and timing needed to program the non-volatile memory is given in Figure 2. It then takes a maximum of 100ms for the programming to be completed inside the device. When the part is programmed, the counter setting is loaded into the non-volatile memory. This value will be loaded from the non-volatile memory during initial power-up or when the CE pin is pulled low. Once the programming is completed, it is recommended that the user float the CTL pin. The CTL pin is internally tied to a resistor network connected to ground. If left floating, the voltage at the CTL pin will equal VDD/2. Under these conditions, no additional pulses will be seen by the Up/Down counter via the CTL pin. To prevent further programming, ground the CE pin. CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the CE pin is high. The board should have an additional ESD protection circuit, with a series 1k Ω resistor and a shunt 0.01µF capacitor connected on the CTL pin, (see Figure 3). To avoid unintentional adjustment, the ISL45042 guarantees to reject CTL pulses shorter than 20µs. During Initial Power-up (only), to avoid the possibility of a false pulse (since the internal comparators come up in an unknown state), the very first CTL pulse is ignored. See Figure 8 for the timing information. CE Pin To adjust the output voltage, the CE pin must be pulled high (VDD). The CE pin has an internal pull-down resistor to prevent unwanted reprogramming of the EEPROM. To minimize current consumption, the impedance of this resistor is high: 400k Ω to 5MΩ (see RINTERNAL in Figure 7). Transitions of the CE pin are recommended to be less than 10µs. Replacing Existing Mechanical Potentiometer Circuits Figure 4 shows the common adjustment mechanical circuits and equivalent replacement with the ISL45042. RSET FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL ISL45042 SET OUT AVDD R1 R2 AVDD ISINK VCOM SINGLE PIXEL CTL CE IN LCD PANEL + - COLUMN DRIVER CTL VOLTAGE TIME 4.9V CTLPT FIGURE 2. EEPROM PROGRAMMING >200µs ISL45042 |
Numéro de pièce similaire - ISL45042_11 |
|
Description similaire - ISL45042_11 |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |