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ADC1213D080C1 Fiches technique(PDF) 11 Page - NXP Semiconductors |
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ADC1213D080C1 Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 42 page xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx [1] Typical values measured at VDDA =3V, VDDD =1.8 V, Tamb =25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA =3V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. 10.2 Clock and digital output timing [1] Typical values measured at VDDA =3V, VDDD =1.8 V, Tamb =25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA =3V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified. IMD intermodulation distortion fi = 3 MHz - 89 -- 89 -- 88 - - 89 - dBc fi = 30 MHz - 88 - - 88- - 88- - 88- dBc fi = 70 MHz - 87 - - 87- - 86- - 86- dBc fi = 170 MHz - 84 - - 85 - - 83 - - 84 - dBc ct(ch) channel crosstalk fi = 70 MHz - 100 - - 100 - - 100 - - 100 - dBc Table 6. Dynamic characteristics[1] …continued Symbol Parameter Conditions ADC1213D065 ADC1213D080 ADC1213D105 ADC1213D125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Table 7. Clock and digital output characteristics[1] Symbol Parameter Conditions ADC1213D065 ADC1213D080 ADC1213D105 ADC1213D125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Clock timing input: pins CLKP and CLKM fclk clock frequency 45 - 65 60 - 80 75 - 105 100 - 125 Msps tlat(data) data latency time clock cycles 307 - 850 250 - 283 190 - 226 160 - 170 ns clk clock duty cycle DCS_EN = logic 1 30 50 70 30 50 70 30 50 70 30 50 70 % DCS_EN = logic 0 45 50 55 45 50 55 45 50 55 45 50 55 % td(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns twake wake-up time -76- -76- -76- -76- s |
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