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FQPPF9N50C Fiches technique(PDF) 9 Page - Fairchild Semiconductor

No de pièce FQPPF9N50C
Description  PFCPWM Combination Controller
Download  17 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FQPPF9N50C Fiches technique(HTML) 9 Page - Fairchild Semiconductor

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AN-8027
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 8/26/09
9
It is typical to set the maximum power limit of PFC stage
around 1.2~1.5 of its nominal power such that the VEA is
around 4~4.5V at nominal output power. By adjusting the
current-sensing resistor for PFC stage, the maximum power
limit of PFC stage can be programmed.
To filter out the current ripple of switching frequency, an
RC filter is typically used for ISENSE pin. RLF1 should not
be larger than 100Ω and the cut-off frequency of filter
should be 1/2~1/6 of the switching frequency.
Diodes D1 and D2 are required to prevent over-voltage on
ISENSE pin due to the inrush current that might damage
the IC. A fast recovery diode or ultra fast recovery diode is
recommended.
Figure 16. Gain Modulation Block
(Design Example)
Setting the maximum power limit
of PFC stage as 450W, the current sensing resistor is
obtained as:
2
23
.
1
6
72 9 5.7 10
0.098
610 450
MAX
LINE BO
M
CS
MAX
IAC BOUT
VG
R
R
RP
⋅⋅
⋅⋅
×
==
=
Ω
×⋅
Thus, 0.1
Ω resistor is selected.
[STEP-8] PFC Current Loop Design
The transfer function from duty cycle to the inductor
current of boost power stage is given as:
=
)
)
BOUT
L
BOOST
V
i
sL
d
(29)
The transfer function from the output of the current control
error amplifier to the inductor current-sensing voltage is
obtained as:
11
=
)
)
CS
CS
BOUT
IEA
RAMP
BOOST
vR
V
vV
sL
(30)
where VRAMP is the peak to peak voltage of ramp signal for
current control PWM comparator, which is 2.55V.
The transfer function of the compensation circuit is given as:
1
1
2
2
1
2
IC
IEA
II
CS
IP
s
f
vf
s
vs
f
π
π
π
+
=⋅
+
)
)
(31)
where:
11
2
1
,
22
1
2
MI
II
IZ
IC
IC
IC
IP
IC
IC
G
f
fand
CR
C
f
RC
ππ
π
==
⋅⋅
=
⋅⋅
(32)
The procedure to design the feedback loop is as follows:
(a) Determine the crossover frequency (fIC) around
1/10~1/6 of the switching frequency. Then calculate
the gain of the transfer function of Equation (30) at
crossover frequency as:
11
@
2
IC
CS
CS
BOUT
IEA
RAMP
IC
BOOST
ff
vR
V
vV
f
L
π
=
=
⋅⋅
)
)
(33)
(b) Calculate RIC that makes the closed loop gain unity at
crossover frequency:
1
@
1
IC
IC
CS
MI
IEA
ff
R
v
G
v
=
=
)
)
(34)
(c) Since the control-to-output transfer function of power
stage has -20dB/dec slope and -90o phase at the
crossover frequency is 0dB, as shown in Figure 17; it
is necessary to place the zero of the compensation
network (fIZ) around 1/3 of the crossover frequency so
that more than 45
° phase margin is obtained. Then the
capacitor CIC1 is determined as:
1
1
2/ 3
IC
IC
C
C
Rf
π
=
(35)
(d) Place compensator high-frequency pole (fCP) at least a
decade higher than fIC to ensure that it does not
interfere with the phase margin of the current loop at
its crossover frequency.
2
1
2
IC
IP
IC
C
fR
π
=
⋅⋅
(36)


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