LC875064B/56B/48B

No.6714-2/26

(2) Random Access Memory (RAM)

- 2048

× 8 bits (LC875064B/56B/48B)

(3) Bus Cycle Time

- 100ns (10MHz)

Note: The bus cycle time indicates ROM read time.

(4) Minimum Instruction Cycle Time

: 300ns (10MHz)

(5) Ports

- Input/output ports

Each bit data direction programmable

51 (P1n, P2n, P70 to P73, P80 to P82, PA2 to PA5,

PBn, PCn)

Nibble data direction programmable

8

(P0n)

- Input ports

2

(XT1,XT2)

- PWM Output ports

2

(PWM0,PWM1)

- Oscillator pins

2

(CF1,CF2)

- Reset pin

1

( RES )

- Power supply

6

(VSS1 to 3,VDD1 to 3)

(6) Timers

- Timer0: 16 bit timer/counter with capture register

Mode 0:

2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register

Mode 1:

8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit

capture register

Mode 2:

16 bit timer with 8 bit programmable prescaler and 16 bit capture register

Mode 3:

16 bit counter with 16 bit capture register

- Timer1: PWM/16 bit timer/counter (with toggle output)

Mode 0:

8 bit timer (with toggle output) + 8 bit timer counter (with toggle output)

Mode 1:

2 channel 8 bit PWM

Mode 2:

16 bit timer/counter (with toggle output)

Mode 3:

16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output.

- Base timer

1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system

clock, and prescaler output for timer 0.

2. Interrupts can be selected to occur at one of five different times.

(7) SIO

- SIO0: 8 bit synchronous serial interface

1. LSB first/MSB first function available

3. Continuous automatic data communications (1 - 256 bits)

- SIO1: 8 bit asynchronous/synchronous serial interface

Mode 0:

Mode 1:

Mode 2:

Mode 3:

Bus mode 2 (start detection, 8 data bits, stop detection)

(8) AD converter

- 8-bits

× 3-channels

(9) PWM

- 2 channel synchronous variable 12 bit PWM

(10) Parallel interface

- RS, RD , WR , CS0 - CS2 Outputs (reversible polarity)