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ISLA212P13 Fiches technique(PDF) 11 Page - Intersil Corporation

No de pièce ISLA212P13
Description  16-Bit, 250MSPS/200MSPS/130MSPS ADC
Download  32 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA212P13 Fiches technique(HTML) 11 Page - Intersil Corporation

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ISLA216P
11
FN7574.0
January 13, 2011
FIGURE 1B. CMOS
FIGURE 1. TIMING DIAGRAMS
Timing Diagrams
CLKN
CLKP
INP
INN
tA
CLKOUT
tCPD
LATENCY = L CYCLES
tDC
tPD
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
D[14/12/…/2/0]
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
1.65
2.4
3.5
ns
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Rising/Falling Edge
-0.1
0.16
0.5
ns
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Rising/Falling Edge
-0.1
0.2
0.65
ns
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
0.4
0.06
ns
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
0.02
0.35
ns
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
DLL recovery time after
Synchronous Reset
52
µs
Latency (Pipeline Delay)
L
10
cycles


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