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LC72722 Fiches technique(PDF) 10 Page - Sanyo Semicon Device |
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LC72722 Fiches technique(HTML) 10 Page - Sanyo Semicon Device |
10 / 15 page No. 5602-10/15 LC72722, 72722M, 72722PM These pins indicate the number of blocks in a set of 48 blocks that had errors before correction. The output polarity of these pins is fixed at the values listed in the table. Mode 4 Pin T6 (BE1) Pin T7 (BE0) Number of error blocks (B) B = 0 Low (0) Low (0) 1 ≤ B ≤ 20 Low (0) High (1) 20 < B ≤ 40 High (1) Low (0) 40 < B ≤ 48 High (1) High (1) Caution: The output indicates the synchronization state for the previous block. Mode (PT2 = 0) The SYNC pin 0 to 2 When synchronized: Low (0). When unsynchronized: High (1) When synchronized: Goes high for a fixed period (421 µs) at 3 the start of a block and then goes low. When unsynchronized: High (1) When PT2 = 0 The RDS-ID pin No RDS High (1) RDS present Low (0) 11. Test mode settings (4 bits): TS0 to TS3 Initial values: TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0 (Applications must set these bits to the above values.) Notes: The T1 and T2 pins (pins 7 and 8) are related to test mode as follows: The T1 pin must be tied to VSS (0 V). Initial values: CT0 = 0, CT1 = 0 Pin T1 Pin T2 LSI operation Notes 0 0 Normal operating mode These states are user settable 0 1 Standby mode (crystal oscillator stopped) 1 0/1 LSI test mode Users cannot use this state 12. Circuit control (2 bits): CT0 and CT1 Item Control CT0 RSFT control When set to 1, soft-decision control data (RSFT) is more difficult to generate. CT1 RDS-ID detection condition When set to 1, the RDS-ID detection conditions are made more restrictive. RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing Timing 1 17 µs 421 µs 421 µs Tp2 Tp1 17 µs RDCL output RSFT output RDDA output A12377 |
Numéro de pièce similaire - LC72722 |
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Description similaire - LC72722 |
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