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LC65P29 Fiches technique(PDF) 10 Page - Sanyo Semicon Device |
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LC65P29 Fiches technique(HTML) 10 Page - Sanyo Semicon Device |
10 / 14 page No. 5894-10/14 LC65P29 Parameter Symbol Applicable Conditions Ratings Unit pins/notes min typ max Maximum supply voltage VDD max VDD –0.3 +7.0 V Output voltage VO OSC2 Values up to the generated voltage are allowed. V VI1 OSC1*1 –0.3 VDD + 0.3 V Input voltage VI2 TEST, RES –0.3 VDD + 0.3 V VI3 Ports with –0.3 VDD + 0.3 V PE specifications I/O voltage VIO PA, PC, PD –0.3 +15 mA Peak output current IOP PA, PC, PD –2 +20 mA IOA PA, PC, PD The 100 ms average per pin –2 +20 mA Average output current Σ IOA1 PA The total current for pins PA0 to PA3*2 –6 +40 mA Σ IOA2 PC, PD The total current for pins PC0 to PC3 and –14 +90 mA PD0 to PD3*3 Allowable power dissipation Pdmax1 Ta = –30 to +70°C(DIP24S) 360 mW Pdmax2 Ta = –30 to +70°C(MFP30S) 150 mW Operating temperature Topr –30 +70 °C Storage temperature Tstg –55 +125 °C Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Applicable Conditions Ratings Unit pins/notes VDD [V] min typ max Operating supply voltage VDD VDD 3.0 6.0 V Standby supply voltage VST VDD RAM and register retention * 1.8 6.0 V VIH1 PA, PC, PD Output n-channel transistor off 0.7 VDD 13.5 V VIH2 PE When the port E input option 0.7 VDD VDD V High-level input voltage is selected VIH3 RES 1.8 to6.0 0.8 VDD VDD V VIH4 OSC1 When the RC oscillator and 0.8 VDD VDD V external clock option is selected VIL1 PA, PC, PD Output n-channel transistor off VSS 0.3 VDD V VIL2 PE When the port E input option VSS 0.3 VDD V is selected Low-level input voltage VIL3 OSC1 When the RC oscillator and VSS 0.25 VDD V external clock option is selected VIL4 TEST VSS 0.3 VDD V VIL5 RES VSS 0.25 VDD V Operating frequency (cycle time) fop(tCYC) 200 (20) 4330 (0.92) kHz (µs) Frequency fext(text) OSC1 See Figure 1 200 (20) 4330 (0.92) kHz (µs) Pulse width textH, textL OSC1 See Figure 1 69 ns Rise and fall times textR, textF OSC1 See Figure 1 50 ns Cext OSC1, OSC2 See Figure 2 4 to 6 220 ±5% pF Two-pin RC oscillator Cext OSC1, OSC2 See Figure 2 220 ±5% pF Rext OSC1, OSC2 See Figure 2 4 to 6 6.8 ±1% k Ω Rext OSC1, OSC2 See Figure 2 15.0 ±1% k Ω Ceramic oscillator See Figure 2 See Table 1 Allowable Operating Conditions at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 6.0 V Notes: 1. Values up to the generated oscillator amplitude are allowed when driven internally using the guaranteed circuit constant values with the oscillator circuit shown in figure 2. 2. The average over a 100 ms period. Note *: Applications must maintain the operating supply voltage (VDD) until the IC has entered the standby state when a HALT instruction is executed. Also, applications must assure that chattering (key bounce) noise is not input to the PA3 pin during a HALT instruction execution cycle. |
Numéro de pièce similaire - LC65P29 |
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Description similaire - LC65P29 |
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