 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
AD21465WBBZ3 Fiches technique(PDF) 5 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD21465WBBZ3 Fiches technique(HTML) 5 Page - Analog Devices |
|
|
5 / 60 page  ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data Rev. PrA | Page 5 of 60 | November 2008 The ADSP-21462W/ADSP-21465W/ADSP-21467 continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram on Page 1 illustrates the following architec- tural features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core pro- cessor cycle • Two programmable interval timers with external event counter capabilities •On-chip SRAM • JTAG test access port • FFT, FIR, IIR accelerators The block diagram of the processor on Page 1 also illustrates the following architectural features: • DMA controller • Digital applications interface that includes four precision clock generators (PCG), an S/PDIF-compatible digital audio receiver/transmitter with four independent asyn- chronous sample rate converters, an input data port (IDP) with eight serial ports, DTCP cipher, eight serial interfaces, a 20-bit parallel input port (PDAP), and a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes two timers, one UART, two serial peripheral interfaces (SPI), a 2-wire interface (TWI), and a flexible signal routing unit (DPI SRU). FAMILY CORE ARCHITECTURE The ADSP-21462W/ADSP-21465W/ADSP-21467 is code com- patible at the assembly level with the ADSP-2137x, ADSP- 2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21462W/ADSP-21465W/ADSP-21467 shares architec- tural features with the ADSP-2126x, ADSP-2136x, ADSP- 2137x, and ADSP-2116x SIMD SHARC processors, as detailed in the following sections. SIMD Computational Engine The ADSP-21462W/ADSP-21465W/ADSP-21467 contains two computational processing elements that operate as a single- instruction, multiple-data (SIMD) engine. The processing ele- ments are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruc- tion is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is trans- ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band- width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele- ments. These computation units support IEEE 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each pro- cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computa- tion units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21462W/ADSP-21465W/ADSP-21467 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on page 1). With the its separate program and data memory buses and on- chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-21462W/ADSP-21465W/ADSP-21467 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selec- tive—only the instructions whose fetches conflict with PM bus |
Numéro de pièce similaire - AD21465WBBZ3 |
|
Description similaire - AD21465WBBZ3 |
|
|
Lien URL |
| Politique de confidentialité |
| ALLDATASHEET.FR |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
