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DAC1208D650 Fiches technique(PDF) 1 Page - NXP Semiconductors |
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DAC1208D650 Fiches technique(HTML) 1 Page - NXP Semiconductors |
1 / 98 page 1. General description The DAC1208D650 is a high-speed 12-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2 ×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA transmitters. Because of its digital on-chip modulation, the DAC1208D650 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. The DAC1208D650 also includes a 2 ×, 4× or 8× clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current. The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1208D650 is 4 and its maximum serial data rate is 3.125 Gbps. The Multiple Device Synchronization (MDS) guarantees maximum skew of one output clock period between several DAC devices. MDS incorporates modes: Master/slave and All slave mode. 2. Features and benefits DAC1208D650 Dual 12-bit DAC; up to 650 Msps; 2 ×, 4× or 8× interpolating with JESD204A interface Rev. 2 — 14 December 2010 Product data sheet Dual 12-bit resolution IMD3: 80 dBc; fs =640 Msps; fo = 140 MHz 650 Msps maximum update rate ACPR: 71 dBc; two carriers WCDMA; fs = 640 Msps; fo = 133 MHz Selectable 2 ×, 4× or 8× interpolation filters Typical 1.22 W power dissipation at 4 × interpolation, PLL off and 640 Msps Input data rate up to 312.5 Msps Power-down mode and Sleep modes Very low-noise cap-free integrated PLL Differential scalable output current from 1.6 mA to 22 mA 32-bit programmable NCO frequency On-chip 1.25 V reference Four JESD204A serial input lanes External analog offset control (10-bit auxiliary DACs) 1.8 V and 3.3 V power supplies Internal digital offset control LVDS compatible clock inputs Inverse (sin x) / x function |
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