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74AHCT30 Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74AHCT30 Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 14 page 74AHC_AHCT30_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 26 June 2009 10 of 14 NXP Semiconductors 74AHC30; 74AHCT30 8-input NAND gate Fig 9. Package outline SOT402-1 (TSSOP14) UNIT A1 A2 A3 bp cD (1) E (2) (1) eHE LLp QZ y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-27 03-02-18 w M b p D Z e 0.25 17 14 8 θ A A1 A2 L p Q detail X L (A ) 3 HE E c v M A X A y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index |
Numéro de pièce similaire - 74AHCT30 |
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Description similaire - 74AHCT30 |
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