HEF4517B_6

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 06 — 10 December 2009

5 of 15

NXP Semiconductors

HEF4517B

Dual 64-bit static shift register

7.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance state;

↑ = positive-going transition; ↓ = negative-going transition.

8.

Limiting values

[1]

[2]

Table 3.

Function table[1]

Inputs

Inputs/outputs

Mode

nCP nD

nPE/OE

nQ16

nQ32

nQ48

nQ64

↑

data entered

into 1st bit

L

content of

16th bit

displayed

content of

32nd bit

displayed

content of

48th bit

displayed

content of

64th bit

displayed

One 64-bit shift register. The

content of the shift register is

shifted over one stage

↑

data entered

into 1st bit

H

data at nQ16

entered into

17th bit

data at nQ32

entered into

33rd bit

data at nQ48

entered into

49th bit

remains in ‘Z’

state

Four 16-bit shift register. The

content of the shift registers is

shifted over one stage

↓

X

L

no change

no change

no change

no change

no change

↓

X

H

ZZZZno change

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.5

+18

V

input clamping current

-

±10

mA

input voltage

−0.5

V

output clamping current

-

±10

mA

input/output current

-

±10

mA

supply current

-

50

mA

storage temperature

−65

+150

°C

ambient temperature

−40

+85

°C

total power dissipation

DIP16 package

[1] -

750

mW

SO16 package

[2] -

500

mW

P

power dissipation

per output

-

100

mW