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ISL22446WFRT20Z Fiches technique(PDF) 2 Page - Intersil Corporation |
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ISL22446WFRT20Z Fiches technique(HTML) 2 Page - Intersil Corporation |
2 / 15 page 2 FN6181.2 September 9, 2009 Block Diagram SPI INTERFACE VCC RH0 RH1 RH2 RH3 GND RL0 RL1 RL2 RL3 RW0 RW1 RW2 RW3 SCK SDI SDO CS WR3 WR2 WR1 WR0 SHDN POWER UP INTERFACE, CONTROL AND STATUS LOGIC NON- VOLATILE REGISTERS Pin Descriptions TSSOP PIN NUMBER TQFN PIN NUMBER SYMBOL DESCRIPTION 1 3 RH3 “High” terminal of DCP3 2 4 RL3 “Low” terminal of DCP3 3 5 RW3 “Wiper” terminal of DCP3 4 6 NC No connect 5 7 SCK SPI clock input 6 8 SDO SPI Open drain Data Output 7 9 GND Device ground pin 8 10 RW2 “Wiper” terminal of DCP2 9 11 RL2 “Low” terminal of DCP2 10 12 RH2 “High” terminal of DCP2 11 13 RW1 “Wiper” terminal of DCP1 12 14 RL1 “Low” terminal of DCP1 13 15 RH1 “High” terminal of DCP1 14 16 CS SPI Chip Select active low input 15 17 SDI SPI Data Input 16 18 VCC Power supply pin 17 19 SHDN Shutdown active low input 18 20 RH0 “High” terminal of DCP0 19 1 RL0 “Low” terminal of DCP0 20 2 RW0 “Wiper” terminal of DCP0 EPAD* Exposed Die Pad internally connected to GND *NOTE: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf ISL22446 |
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