CC2510FX_10 datasheet(58/244 Pages) TI

No de pièce	CC2510FX

Description	Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

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58 / 244 page

CC2510Fx / CC2511Fx

SWRS055F

Page 58 of 241

4. Enable global interrupt by setting the

IEN0.EA=1

5. Begin the interrupt service routine at the

corresponding vector address of that

interrupt. See

Table

39

for

addresses

Interrupt

Number

Description

Interrupt

Name

Interrupt

Vector

CPU Interrupt

Mask

CPU Interrupt Flag

0

RF TX done / RX ready

RFTXRX

0x03

IEN0.RFTXRXIE

TCON.RFTXRXIF10

1

ADC end of conversion

ADC

0x0B

IEN0.ADCIE

TCON.ADCIF10

2

USART0 RX complete

URX0

0x13

IEN0.URX0IE

TCON.URX0IF10

3

USART1 RX complete

(Note: I

2S RX complete, see Table

40

)

URX1

0x1B

IEN0.URX1IE

TCON.URX1IF10

4

AES encryption/decryption

complete

ENC

0x23

IEN0.ENCIE

S0CON.ENCIF

5

Sleep Timer compare

ST

0x2B

IEN0.STIE

IRCON.STIF11

6

Port 2 inputs

(Note: Also used for USB on

CC2511Fx,, see Table 40)

P2INT

0x33

IEN2.P2IE

IRCON2.P2IF11

7

USART0 TX complete

UTX0

0x3B

IEN2.UTX0IE

IRCON2.UTX0IF

8

DMA transfer complete

DMA

0x43

IEN1.DMAIE

IRCON.DMAIF

9

Timer 1 (16-bit)

capture/Compare/overflow

T1

0x4B

IEN1.T1IE

IRCON.T1IF10,11

10

Timer 2 (MAC Timer) overflow

T2

0x53

IEN1.T2IE

IRCON.T2IF10, 11

11

Timer 3 (8-bit) compare/overflow

T3

0x5B

IEN1.T3IE

IRCON.T3IF10, 11

12

Timer 4 (8-bit) compare/overflow

T4

0x63

IEN1.T4IE

IRCON.T4IF10, 11

13

Port 0 inputs

(Note: P0_7 interrupt used for USB

Resume interrupt on

CC2511Fx)

P0INT

0x6B

IEN1.P0IE

IRCON.P0IF11

14

USART1 TX complete

(Note: I

2S TX complete, see Table

40

)

UTX1

0x73

IEN2.UTX1IE

IRCON2.UTX1IF

15

Port 1 inputs

P1INT

0x7B

IEN2.P1IE

IRCON2.P1IF11

16

RF general interrupts

RF

0x83

IEN2.RFIE

S1CON.RFIF11

17

Watchdog overflow in timer mode

WDT

0x8B

IEN2.WDTIE

IRCON2.WDTIF

Table 39: Interrupts Overview

10 Cleared by HW when the CPU vectors to the ISR

11 Additional interrupt mask bits and/or interrupt flags found in the peripheral’s SFRs

Note: An interrupt must not be enabled

without having proper code located at the

corresponding interrupt vector address

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