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ISL12028IVZ Fiches technique(PDF) 6 Page - Intersil Corporation

No de pièce ISL12028IVZ
Description  Real Time Clock/Calendar with I2C Bus??and EEPROM
Download  29 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12028IVZ Fiches technique(HTML) 6 Page - Intersil Corporation

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6
FN8233.8
August 9, 2010
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VDD,
until SDA exits the 30% to 70% of VDD
window.
900
ns
tBUF
Time the bus must be free before
the start of a new transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30%
of VDD to SCL falling edge crossing
70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 70%
of VDD to SDA entering the 30% to
70% of VDD window.
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
0
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Cpin
SDA, and SCL Pin Capacitance
10
pF
tWC
Non-volatile Write Cycle Time
12
20
ms
14
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 + 0.1 x Cb
250
ns
15
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 + 0.1 x Cb
250
ns
15
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
15
RPU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about
2k
Ω~2.5kΩ.
For Cb = 40pF, max is about
15k
Ω~20kΩ
1
k
Ω
15
NOTES:
7. IRQ/FOUT Inactive (no frequency output and no alarms).
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥ 1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Serial Interface (I2C) Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNITS
NOTES
ISL12028, ISL12028A


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