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KM62256CLTG-5 Fiches technique(PDF) 5 Page - Samsung semiconductor

No de pièce KM62256CLTG-5
Description  32Kx8 bit Low Power CMOS Static RAM
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Fabricant  SAMSUNG [Samsung semiconductor]
Site Internet  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM62256CLTG-5 Fiches technique(HTML) 5 Page - Samsung semiconductor

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PRELIMINARY
Revision 3.0
KM62256C Family
CMOS SRAM
April 1996
TEST CONDITIONS(2. Temperature and Vcc Conditions)
* The parameter is measured with 30pF test load
Product Family
Temperature
Power Supply(Vcc)
Speed Bin
Comments
KM62256CL/L-L
0~70¡É
5V ¡¾ 10%
45*/55/70ns
Commercial
KM62256CLE/LE-L
-25~85¡É
5V ¡¾ 10%
70/100ns
Extended
KM62256CLI/LI-L
-40~85¡É
5V ¡¾ 10%
70/100ns
Industrial
PARAMETER LIST FOR EACH SPEED BIN
* The parameter is measured with 30pF test load
Parameter List
Symbol
Speed Bins
Units
45ns*
55ns
70ns
100ns
Min
Max
Min
Max
Min
Max
Min
Max
Read
Read cycle time
tRC
45
-
55
-
70
-
100
-
ns
Address access time
tAA
-
45
-
55
-
70
-
100
ns
Chip select to output
tCO
-
45
-
55
-
70
-
100
ns
Output enable to valid output
tOE
-
25
-
25
-
35
-
50
ns
Chip select to low-Z output
tLZ
10
-
10
-
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
5
-
5
-
ns
Chip disable to high-Z output
tHZ
0
20
0
20
0
30
0
35
ns
Output disable to high-Z output
tOHZ
0
20
0
20
0
30
0
35
ns
Output hold from address change
tOH
5
-
5
-
5
-
5
-
ns
Write
Write cycle time
tWC
45
-
55
-
70
-
100
-
ns
Chip select to end of write
tCW
45
-
45
-
60
-
80
-
ns
Address set-up time
tAS
0
-
0
-
0
-
0
-
ns
Address valid to end of write
tAW
45
-
45
-
60
-
80
-
ns
Write pulse width
tWP
40
-
40
-
50
-
60
-
ns
Write recovery time
tWR
0
-
0
-
0
-
0
-
ns
Write to output high-Z
tWHZ
0
20
0
20
0
25
0
35
ns
Data to write time overlap
tDW
25
-
25
-
30
-
50
-
ns
Data hold from write time
tDH
0
-
0
-
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
5
-
5
-
ns


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