KM681002B, KM681002BI

CMOS SRAM

PRELIMINARY

Rev 2.0

- 4 -

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

TEST CONDITIONS

Parameter

Value

Input Pulse Levels

0V to 3V

Input Rise and Fall Times

3ns

Input and Output timing Reference Levels

1.5V

Output Loads

See below

READ CYCLE

NOTE: The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

KM681002B-8

KM681002B-10

KM681002B-12

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

8

-

10

-

12

-

ns

Address Access Time

-

8

-

10

-

12

ns

Chip Select to Output

-

8

-

10

-

12

ns

Output Enable to Valid Output

-

4

-

5

-

6

ns

Chip Enable to Low-Z Output

3

-

3

-

3

-

ns

Output Enable to Low-Z Output

0

-

0

-

0

-

ns

Chip Disable to High-Z Output

0

4

0

5

0

6

ns

Output Disable to High-Z Output

0

4

0

5

0

6

ns

Output Hold from Address Change

3

-

3

-

3

-

ns

Chip Selection to Power Up Time

0

-

0

-

0

-

ns

Chip Selection to Power DownTime

-

8

-

10

-

12

ns

Output Loads(B)

5pF*

480

Ω

255

Ω

+5.0V

* Including Scope and Jig Capacitance

Output Loads(A)

Ω

Ω

30pF*

* Capacitive Load consists of all components of the

test environment.