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74ALVT16501DL Fiches technique(PDF) 7 Page - NXP Semiconductors |
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74ALVT16501DL Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 20 page 74ALVT16501_4 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 04 — 8 August 2005 7 of 20 Philips Semiconductors 74ALVT16501 18-bit universal bus transceiver; 3-state 7. Functional description 7.1 Function table [1] H = HIGH voltage level; h = HIGH voltage level one setup time prior to the enable or clock transition; L = LOW voltage level; I = LOW voltage level one setup time prior to the enable or clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↓ = HIGH-to-LOW enable or clock transition; ↑ = LOW-to-HIGH enable or clock transition. VCC 50 voltage supply B2 51 data input or output (B side) B1 52 data input or output (B side) GND 53 ground (0 V) B0 54 data input or output (B side) CPAB 55 A-to-B clock input (active rising edge) GND 56 ground (0 V) Table 3: Pin description …continued Symbol Pin Description Table 4: Function table [1] Operating mode Control Input Internal registers Output OEAB LEAB CPAB An Bn OEBA LEBA CPBA Bn An Disabled L H XXXZ Disabled, latch data L ↓ Xh H Z lL Z Disabled, hold data L L H or L X NC Z Disabled, clock data L L ↑ hH Z lL Z Transparent H H X H H H LLL Latch data and display H ↓ Xh H H lL L Clock data and display H L ↑ hH H lL L Hold data and display H L H or L X H H XL L |
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Description similaire - 74ALVT16501DL |
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