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TEA1752T Fiches technique(PDF) 6 Page - NXP Semiconductors |
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TEA1752T Fiches technique(HTML) 6 Page - NXP Semiconductors |
6 / 34 page TEA1752T_LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 24 June 2010 6 of 34 NXP Semiconductors TEA1752T; TEA1752LT GreenChip III SMPS control IC 7. Functional description 7.1 General control The TEA1752(L)T contains controllers for a power factor correction circuit and for a flyback circuit. A typical configuration is shown in Figure 3. 7.1.1 Start-up and UnderVoltage LockOut (UVLO) Initially the capacitor on the VCC pin is charged from the high voltage mains via the HV pin. If VCC is lower than Vtrip, the charge current is low. This protects the IC if the VCC pin is shorted to ground. The charge current above Vtrip is increased until VCC reaches Vth(UVLO) to achieve a short start-up time. If VCC is between Vth(UVLO) and Vstartup, the charge current is low again, ensuring a low duty cycle during fault conditions. The control logic activates the internal circuitry and switches off the HV charge current when the voltage on pin VCC passes the Vstartup level. The LATCH pin current source is then activated and the soft start capacitors on pins PFCSENSE and FBSENSE are charged and the clamp circuit on pin PFCCOMP is activated. When the LATCH pin voltage exceeds Ven(LATCH), the PFCCOMP pin voltage exceeds Ven(PFCCOMP) and the soft start capacitor on pin PFCSENSE pin is charged, the PFC circuit is activated. The flyback Fig 3. Typical configuration 12 11 9 16 13 8 6 7 3 10 4 1 TEA1752(L)T 014aaa750 Θ D2 T2 5 D1 S1 compensation S2 2 14 RAUX1 CSS1 RSS1 Cbus RSENSE1 RS1 RS2 RAUX2 COUT RSS2 CSS2 CVCC RSENSE2 RLOOP CTIMEOUT VCC GND PFCTIMER FBCTRL FBAUX LATCH PFCCOMP PFCAUX PFCSENSE FBTIMER VOSENSE HV FBSENSE PFCDRIVER VINSENSE |
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