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UC2825AQ Fiches technique(PDF) 3 Page - Texas Instruments |
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UC2825AQ Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 18 page UC1823A,UC2823A, UC2823B, UC3823A,UC3823B,UC1825A, UC2825A,UC2825B,UC3825A,UC3825B SLUS334D − AUGUST 1995 − REVISED NOVEMBER 2008 www.ti.com 3 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION NAME J or DW Q or L I/O DESCRIPTION CLK/LEB 4 5 O Output of the internal oscillator CT 6 8 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. EAOUT 3 4 O Output of the error amplifier for compensation GND 10 13 − Analog ground return pin ILIM 9 12 I Input to the current limit comparator INV 1 2 I Inverting input to the error amplifier NI 2 3 I Non-inverting input to the error amplifier OUTA 11 14 O High current totem pole output A of the on-chip drive stage. OUTB 14 18 O High current totem pole output B of the on-chip drive stage. PGND 12 15 − Ground return pin for the output driver stage RAMP 7 9 I Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. RT 5 7 I Timing resistor connection pin for oscillator frequency programming SS 8 10 I Soft-start input pin which also doubles as the maximum duty cycle clamp. VC 13 17 − Power supply pin for the output stage. This pin should be bypassed with a 0.1- µF monolithic ceramic low ESL capacitor with minimal trace lengths. VCC 15 19 − Power supply pin for the device. This pin should be bypassed with a 0.1- µF monolithic ceramic low ESL capacitor with minimal trace lengths VREF 16 20 O 5.1-V reference. For stability, the reference should be bypassed with a 0.1- µF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT VIN Supply voltage, VC, VCC 22 V IO Source or sink current, DC OUTA, OUTB 0.5 A IO Source or sink current, pulse (0.5 µs) OUTA, OUTB 2.2 A Analog inputs INV, NI, RAMP −0.3 V to 7 V Analog inputs ILIM, SS −0.3 V to 6 V Power ground PGND ±0.2 V Outputs OUTA, OUTB limits PGND −0.3 V to VC +0.3 V ICLK Clock output current CLK/LEB −5 mA IO(EA) Error amplifier output current EAOUT 5 mA ISS Soft-start sink current SS 20 mA IOSC Oscillator charging current RT −5 mA TJ Operating virtual junction temperature range −55 °C to 150°C Tstg Storage temperature −65 °C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds −55C °C to 150°C tSTG Storage temperature −65 °C to 150°C Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. |
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