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TL16C2550PFBRG4 Fiches technique(PDF) 5 Page - Texas Instruments

No de pièce TL16C2550PFBRG4
Description  1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
Download  47 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TL16C2550PFBRG4 Fiches technique(HTML) 5 Page - Texas Instruments

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Detailed Description
Autoflow Control (see Figure 1)
TL16C2550
SLWS161D – JUNE 2005 – REVISED OCTOBER 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
PFB NO.
FN NO.
RHB NO.
Ring indicator (active low). These inputs are associated with individual
UART channels A and B. A logic low on these pins indicates the modem
has received a ringing signal from the telephone line. A low to high
RIA, RIB
41, 21
43, 26
I
transition on these input pins generates a modem status interrupt, if
enabled. The state of these inputs is reflected in the modem status register
(MSR)
Request to send (active low). These outputs are associated with individual
UART channels A and B. A low on the RTS pin indicates the transmitter
has data ready and waiting to send. Writing a 1 in the modem control
RTSA,
register (MCR bit 1) sets these pins to low, indicating data is available.
33, 22
36, 27
23, 15
O
RTSB
After a reset, these pins are set to high. These pins only affects the
transmit and receive operation when auto RTS function is enabled through
the enhanced feature register (EFR) bit 6, for hardware flow control
operation.
Receive data input. These inputs are associated with individual serial
channel data to the 2550. During the local loopback mode, these RX input
RXA, RXB
5, 4
11, 10
4, 3
I
pins are disabled and TX data is internally connected to the UART RX input
internally.
Receive ready (active low). RXRDY A and B goes low when the trigger
RXRDYA,
31, 18
34, 23
O
level has been reached or a timeout interrupt occurs. They go high when
RXRDYB
the RX FIFO is empty or there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit
TXA, TXB
7, 8
13, 14
5, 6
O
channel data from the 2550. During the local loopback mode, the TX input
pin is disabled and TX data is internally connected to the UART RX input.
Transmit ready (active low). TXRDY A and B go low when there are at least
TXRDYA,
43, 6
1, 12
O
a trigger level numbers of spaces available. They go high when the TX
TXRDYB
buffer is full.
VCC
42
44
26
I
Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an
external clock input. A crystal can be connected between XTAL1 and
XTAL1
13
18
10
I
XTAL2 to form an internal oscillator circuit (see Figure 14). Alternatively, an
external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is
XTAL2
14
19
11
O
used as a crystal oscillator output or buffered a clock output.
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data
and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless
the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2550 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
5
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