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CDCE937 Fiches technique(PDF) 6 Page - Texas Instruments |
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CDCE937 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 30 page CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT OVERALL PARAMETER All PLLS on 29 All outputs off, f(CLK) = 27 MHz, IDD Supply current (see Figure 3) mA f(VCO) = 135 MHz Per PLL 9 CDCE937, 3.1 VDDOUT = 3.3 V Output supply current (see Figure 4 and No load, all outputs on, IDDOUT mA Figure 5 fOUT = 27 MHz CDCEL937, 1.5 VDDOUT = 1.8 V Power-down current. Every circuit powered IDD(PD) fIN = 0 MHz, VDD = 1.9 V 50 mA down except SDA/SCL Supply voltage Vdd threshold for power-up V(PUC) 0.85 1.45 V control circuit f(VCO) VCO frequency range of PLL 80 230 MHz Vddout = 3.3 V 230 fOUT LVCMOS output frequency MHz Vddout = 1.8 V 230 LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V; II = –18 mA –1.2 V II LVCMOS Input current VI = 0 V or VDD; VDD = 1.9 V ±5 mA IIH LVCMOS Input current for S0/S1/S2 VI = VDD; VDD = 1.9 V 5 mA IIL LVCMOS Input current for S0/S1/S2 VI = 0 V; VDD = 1.9 V –4 mA Input capacitance at Xin/Clk VI(Clk) = 0 V or VDD 6 CI Input capacitance at Xout VI(Xout) = 0 V or VDD 2 pF Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3 CDCE937 - LVCMOS PARAMETER FOR Vddout = 3.3 V – MODE Vddout = 3 V, IOH = –0.1 mA 2.9 VOH LVCMOS high-level output voltage Vddout = 3 V, IOH = –8 mA 2.4 V Vddout = 3 V, IOH = –12 mA 2.2 Vddout = 3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage Vddout = 3 V, IOL = 8 mA 0.5 V Vddout = 3 V, IOL = 12 mA 0.8 tPLH, Propagation delay All PLL bypass 3.2 ns tPHL tr/tf Rise and fall time Vddout= 3.3 V (20%–80%) 0.6 ns 1 PLL switching, Y2-to-Y3 60 90 tjit(cc) Cycle-to-cycle jitter(2) (3) ps 3 PLL switching, Y2-to-Y7 100 150 1 PLL switching, Y2-to-Y3 70 100 tjit(per) Peak-to-peak period jitter(3) ps 3 PLL switching, Y2-to-Y7 120 180 fOUT = 50 MHz; Y1-to-Y3 60 tsk(o) Output skew (4) , See Table 2 ps fOUT = 50 MHz; Y2-to-Y5 160 odc Output duty cycle (5) fVCO = 100 MHz; Pdiv = 1 45% 55% (1) All typical values are at respective nominal VDD. (2) 10000 cycles. (3) Jitter depends on configuration. Data is taken under the following conditions: 1-PLL : fIN = 27MHz, Y2/3 = 27 MHz, (measured at Y2), 3-PLL: fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz (4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data taking on rising edge (tr). (5) odc depends on output rise and fall time (tr/tf). 6 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 |
Numéro de pièce similaire - CDCE937_10 |
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Description similaire - CDCE937_10 |
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