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SN74AUP1G14DBVRE4 Fiches technique(PDF) 2 Page - Texas Instruments |
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SN74AUP1G14DBVRE4 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 22 page AUP LVC AUP AUP LVC Static-Power Consumption ( µA) Dynamic-Power Consumption (pF) † Single, dual, and triple gates 3.3-V Logic† 3.3-V Logic† 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% −0.5 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 Time − ns † AUP1G08 data at C L = 15 pF Output Input Switching Characteristics at 25 MHz† A Y 2 4 A Y 1 3 SN74AUP1G14 SCES578I – JUNE 2003 – REVISED MAY 2010 www.ti.com Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) ORDERABLE PART TOP-SIDE TA PACKAGE(2) NUMBER MARKING(3) NanoStar – WCSP (DSBGA) Reel of 3000 SN74AUP1G14YFPR _ _ _ HF_ 0.23-mm large bump – YFP NanoStar – WCSP (DSBGA) Reel of 3000 SN74AUP1G14YZPR _ _ _ HF_ 0.23-mm large bump – YZP (Pb-free) QFN – DRY Reel of 5000 SN74AUP1G14DRYR HF –40°C to 85°C uQFN – DSF Reel of 5000 SN74AUP1G14DSFR HF SOT (SOT-23) – DBV Reel of 3000 SN74AUP1G14DBVR H14_ SOT (SC-70) – DCK Reel of 3000 SN74AUP1G14DCKR HF_ SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G14DRLR HF_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUT OUTPUT A Y H L L H LOGIC DIAGRAM (POSITIVE LOGIC) (DBV, DCK, DRL, DRT, DRY, and YZP PACKAGES) LOGIC DIAGRAM (POSITIVE LOGIC) (YFP PACKAGE) 2 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G14 |
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