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LM3S9L97-EQN20-C1T Fiches technique(PDF) 5 Page - Texas Instruments |
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LM3S9L97-EQN20-C1T Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 1219 page 8.6 Memory Register Descriptions (System Control Offset) .................................................. 252 9 Micro Direct Memory Access (μDMA) ................................................................ 270 9.1 Block Diagram ............................................................................................................ 271 9.2 Functional Description ................................................................................................. 271 9.2.1 Channel Assignments .................................................................................................. 272 9.2.2 Priority ........................................................................................................................ 273 9.2.3 Arbitration Size ............................................................................................................ 273 9.2.4 Request Types ............................................................................................................ 273 9.2.5 Channel Configuration ................................................................................................. 274 9.2.6 Transfer Modes ........................................................................................................... 276 9.2.7 Transfer Size and Increment ........................................................................................ 284 9.2.8 Peripheral Interface ..................................................................................................... 284 9.2.9 Software Request ........................................................................................................ 284 9.2.10 Interrupts and Errors .................................................................................................... 285 9.3 Initialization and Configuration ..................................................................................... 285 9.3.1 Module Initialization ..................................................................................................... 285 9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 285 9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 287 9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 288 9.3.5 Configuring Channel Assignments ................................................................................ 291 9.4 Register Map .............................................................................................................. 291 9.5 μDMA Channel Control Structure ................................................................................. 292 9.6 μDMA Register Descriptions ........................................................................................ 299 10 General-Purpose Input/Outputs (GPIOs) ........................................................... 328 10.1 Signal Description ....................................................................................................... 328 10.2 Functional Description ................................................................................................. 332 10.2.1 Data Control ............................................................................................................... 334 10.2.2 Interrupt Control .......................................................................................................... 335 10.2.3 Mode Control .............................................................................................................. 336 10.2.4 Commit Control ........................................................................................................... 336 10.2.5 Pad Control ................................................................................................................. 337 10.2.6 Identification ............................................................................................................... 337 10.3 Initialization and Configuration ..................................................................................... 337 10.4 Register Map .............................................................................................................. 338 10.5 Register Descriptions .................................................................................................. 341 11 General-Purpose Timers ...................................................................................... 384 11.1 Block Diagram ............................................................................................................ 385 11.2 Signal Description ....................................................................................................... 385 11.3 Functional Description ................................................................................................. 388 11.3.1 GPTM Reset Conditions .............................................................................................. 388 11.3.2 32-Bit Timer Operating Modes ...................................................................................... 388 11.3.3 16-Bit Timer Operating Modes ...................................................................................... 390 11.3.4 DMA Operation ........................................................................................................... 395 11.4 Initialization and Configuration ..................................................................................... 395 11.4.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 395 11.4.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 396 11.4.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 396 11.4.4 Input Edge-Count Mode ............................................................................................... 397 5 June 15, 2010 Texas Instruments-Advance Information Stellaris® LM3S9L97 Microcontroller |
Numéro de pièce similaire - LM3S9L97-EQN20-C1T |
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Description similaire - LM3S9L97-EQN20-C1T |
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