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DAC7728SPAGR Fiches technique(PDF) 4 Page - Texas Instruments

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No de pièce DAC7728SPAGR
Description  Octal, 12-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

DAC7728SPAGR Fiches technique(HTML) 4 Page - Texas Instruments

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DAC7728
SBAS461A – JUNE 2009 – REVISED NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values
(1), unless otherwise noted.
DAC7728
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT (VOUT-0 to VOUT-7)
(3)
VREF = +5V
–15
+15
V
Voltage output(4)
VREF = +1.5V
–4.5
+4.5
V
Output impedance
Code = 800h
0.5
Short-circuit current(5)
±10
mA
Load current
See Figure 37
±3
mA
TA = +25°C, Device operating for 500 hours, full-scale output
3.4
ppm of FSR
Output voltage drift vs time
TA = +25°C, Device operating for 1000 hours, full-scale
4.3
ppm of FSR
output
Capacitive load stability
500
pF
To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 000h to
10
μs
FFFh and FFFh to 000h
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 000h to FFFh
Settling time
15
μs
and FFFh to 000h
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 7C0h to 840h
6
μs
and 840h to 7C0h
Slew rate (6)
6
V/
μs
Power-on delay(7)
From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low
200
μs
Power-down recovery time
50
μs
Digital-to-analog glitch(8)
Code from 7FFh to 800h and 800h to 7FFh
4
nV-s
Glitch impulse peak amplitude
Code from 7FFh to 800h and 800h to 7FFh
5
mV
Channel-to-channel isolation(9)
VREF = 4VPP, f = 1kHz
88
dB
DACs in the same group
10
nV-s
DAC-to-DAC crosstalk(10)
DACs among different groups
1
nV-s
Digital crosstalk(11)
1
nV-s
Digital feedthrough(12)
1
nV-s
TA = +25°C at 10kHz, gain = 6
200
nV/
√Hz
Output noise
TA = +25°C at 10kHz, gain = 4
130
nV/
√Hz
0.1Hz to 10Hz, gain = 6
20
μVPP
Power-supply rejection(13)
AVDD = ±15.5V to ±16.5V
0.05
LSB
(3)
Specified by design.
(4)
The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF – 5 × OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of
the analog output must not be greater than (AVDD – 0.5V), and the minimum value must not be less than (AVSS + 0.5V). All
specifications are for a ±16.5V power supply and a ±15V output, unless otherwise noted.
(5)
When the output current is greater than the specification, the current is clamped at the specified maximum value.
(6)
Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(7)
Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(8)
Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFh and 800h in straight binary format.
(9)
Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
(10) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
(11) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
(12) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
(13) The output must not be greater than (AVDD – 0.5V) and not less than (AVSS + 0.5V).
4
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