1

2

SCL

3

4

5

6

7

8

SDA

A

A

A

Data 0

R/W

t

pv

9

0

0

0

0

0

0

0

1

0.7

0.0

Data 1

1.7

1.0 A

S

0

1

0

0

0

0

AD

DR

0

P

Slave Address

Command Byte

Data to Port 0

Data to Port 1

Start Condition

Acknowledge

From Slave

Write to Port

Data Out from Port 1

Data Out from Port 0

Data Valid

Acknowledge

From Slave

Acknowledge

From Slave

t

pv

1

2

SCL

3

4

5

6

7

8

SDA

A

A

A

Data0

Datat Register

o

R/W

9

0/1

0

0

0

0

0

1 1/0

MSB

LSB

Data1

MSB

LSB A

S

0

1

0

0

0

0 AD

DR 0

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

P

Acknowledge

FromSlave

Acknowledge

FromSlave

StartCondition

CommandByte

Slave Address

Acknowledge

FromSlave

Datat Register

o

Reads

TCA6416

Figure 6. Write to Output Port Register

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Figure 7. Write to Configuration or Polarity Inversion Registers

The bus master first must send the TCA6416 address with the LSB set to a logic 0 (see Figure 4 for device

address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register

defined by the command byte then is sent by the TCA6416 (see Figure 8 and Figure 9).

After a restart, the value of the register defined by the command byte matches the register being accessed when

the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart

occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original

command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the

register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but

the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next

byte read is Input Port 0.

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number

of data bytes received in one read transmission, but when the final byte is received, the bus master must not

acknowledge the data.

Copyright © 2007–2009, Texas Instruments Incorporated

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