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SN74LV165APWT Fiches technique(PDF) 2 Page - Texas Instruments |
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SN74LV165APWT Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 22 page SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/ LD is held high. The parallel inputs to the register are enabled while SH/ LD is held low, independently of the levels of CLK, CLK INH, or SER. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS OPERATION SH/ LD CLK CLK INH OPERATION L X X Parallel load H HX Q0 H XH Q0 H L ↑ Shift H ↑ L Shift logic diagram (positive logic) S 1D R C1 S 1D R C1 S 1D R C1 S 1D R C1 S 1D R C1 S 1D R C1 S 1D R C1 S 1D R C1 1 15 2 10 SH/LD CLK INH CLK SER 9 7 QH QH 11 12 13 14 3 4 5 6 AB CD E F G H Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. |
Numéro de pièce similaire - SN74LV165APWT |
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Description similaire - SN74LV165APWT |
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