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CDCEL925PWG4 Fiches technique(PDF) 4 Page - Texas Instruments

No de pièce CDCEL925PWG4
Description  PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS
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Site Internet  http://www.ti.com
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CDCEL925PWG4 Fiches technique(HTML) 4 Page - Texas Instruments

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CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VDD
Device supply voltage
1.7
1.8
1.9
V
Output Yx supply voltage for CDCE925
2.3
3.6
VDDOUT
Output Yx supply voltage for CDCEL925
1.7
1.9
V
VIL
Low-level input voltage LVCMOS
0.3 VDD
V
VIH
High-level input voltage LVCMOS
0.7 VDD
V
VI(thresh)
Input voltage threshold LVCMOS
0.5 VDD
V
Input voltage range S0
0
1.9
VI(S)
V
Input voltage range S1, S2, SDA, SCL; V(Ithresh) = 0.5 VDD
0
3.6
VI(CLK)
Input voltage range CLK
0
1.9
V
Output current (VDDOUT = 3.3 V)
±12
IOH /IOL
Output current (VDDOUT = 2.5 V)
±10
mA
Output current (VDDOUT = 1.8 V)
±8
CL
Output load LVCMOS
15
pF
TA
Operating free-air temperature
–40
85
°C
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS
(1)
MIN
NOM
MAX
UNIT
fXtal
Crystal input frequency range (fundamental mode)
8
27
32
MHz
ESR
Effective series resistance
100
fPR
Pulling range (0 V
≤ VCtrl ≤ 1.8 V)
(2)
±120
±150
ppm
VCtrl
Frequency control voltage
0
VDD
V
C0/C1
Pullability ratio
220
CL
On-chip load capacitance at Xin and Xout
0
20
pF
(1)
For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).
(2)
Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in the application report (SCAA085).
EEPROM SPECIFICATION
MIN
TYP
MAX
UNIT
EEcyc
Programming cycles of EEPROM
100
1000
cycles
EEret
Data retention
10
years
4
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925


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