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SN74AUP1G57DRYR Fiches technique(PDF) 3 Page - Texas Instruments |
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SN74AUP1G57DRYR Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 24 page A Y B 1 2 3 6 5 4 A Y B VCC A Y B A Y B 1 2 3 6 5 4 A Y B VCC A Y B A Y B 1 2 3 6 5 4 A Y B VCC A Y B A Y B 1 2 3 6 5 4 A Y B VCC A Y B 1 2 3 6 5 4 A Y B VCC Y A B SN74AUP1G57 www.ti.com SCES503I – NOVEMBER 2003 – REVISED MAY 2010 FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND 1 2-input AND with both inputs inverted 4 2-input NAND with inverted input 2, 3 2-input OR with inverted input 2, 3 2-input NOR 4 2-input NOR with both inputs inverted 1 2-input XNOR 5 LOGIC CONFIGURATIONS Figure 1. 2-Input AND Gate Figure 2. 2-Input NAND Gate With Inverted A Input Figure 3. 2-Input NAND Gate With Inverted B Input Figure 4. 2-Input NOR Gate Figure 5. 2-Input XNOR Gate Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): SN74AUP1G57 |
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