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TPS40304A

www.ti.com

SLUSA30 – FEBRUARY 2010

Soft-Start Time

The soft-start time of the TPS40304A is user programmable by selecting a single capacitor. The EN/SS pin

sources 10 µA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the

10 µA to charge the capacitor through a 591-mV range. There is some initial lag due to calibration and an offset

(800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.

The soft-start is done in a closed loop fashion, meaning that the error amplifier controls the output voltage at all

times during the soft start period and the feedback loop is never open as occurs in duty cycle limit soft-start

schemes. The error amplifier has two non-inverting inputs, one connected to the 591-mV reference voltage, and

the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier

controls the FB pin to. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800 mV offset

voltage plus the 591-mV reference voltage), the 591-mV reference voltage becomes the dominant input and the

converter has reached its final regulation voltage.

The capacitor required for a given soft-start ramp time for the output voltage is given by Equation 1.

where

•

•

•

•

(1)

Oscillator and Frequency Spread Spectrum (FSS)

The oscillator frequency is internally fixed at 600 kHz.

Connecting a resistor with a value of 267 k

Ω ± 10% from BP to EN/SS enables the FSS feature. When enabled,

it spreads the internal oscillator frequency over a minimum 12% window using a 25-kHz modulation frequency

with triangular profile. By modulating the switching frequency, side-bands are created. The emission power of the

fundamental switching frequency and its harmonics is distributed into smaller pieces scattered around many

side-band frequencies. The effect significantly reduces the peak EMI noise and makes it much easier for the

resultant emission spectrum to pass EMI regulations.

Overcurrent Protection

Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature

coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases.

With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The

accuracy of the internal current source is ±5%. Overall offset voltage, including the offset voltage of the internal

comparator and the amplifier for scale factor of 2, is limited to ±8 mV.

Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a

pre-biased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the

included), it disables OCP. Once disabled, there is no low-side or high-side current sensing.

OCP level at HDRV is fixed at 450 mV with 3000 ppm temperature coefficient to help compensate for changes in

the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current

limiting.

Copyright © 2010, Texas Instruments Incorporated

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