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CAT28LV65GI-25T Fiches technique(PDF) 3 Page - ON Semiconductor |
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CAT28LV65GI-25T Fiches technique(HTML) 3 Page - ON Semiconductor |
3 / 15 page CAT28LV65 http://onsemi.com 3 ADDR. BUFFER & LATCHES ADDR. BUFFER & LATCHES INADVERTENT CONTROL LOGIC TIMER HIGH VOLTAGE GENERATOR I/O BUFFERS 32 BYTE PAGE REGISTER WRITE PROTECTION ROW DECODER COLUMN DECODER Figure 1. Block Diagram CE OE WE VCC A0−A4 A5−A12 RDY/BUSY DATA POLLING RDY/BUSY & TOGGLE BIT I/O0−I/O7 8,192 x 8 E2PROM ARRAY Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Temperature Under Bias –55 to +125 °C Storage Temperature –65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) –2.0 V to +VCC + 2.0 V V VCC with Respect to Ground −2.0 to +7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 secs) 300 °C Output Short Circuit Current (Note 2) 100 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. Table 2. RELIABILITY CHARACTERISTICS (Note 3) Symbol Parameter Test Method Min Max Units NEND Endurance MIL−STD−883, Test Method 1033 105 Cycles/Byte TDR Data Retention MIL−STD−883, Test Method 1008 100 Years VZAP ESD Susceptibility MIL−STD−883, Test Method 3015 2,000 V ILTH (Note 4) Latch−Up JEDEC Standard 17 100 mA 3. These parameters are tested initially and after a design or process change that affects the parameters. 4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V. Table 3. MODE SELECTION Mode CE WE OE I/O Power Read L H L DOUT ACTIVE Byte Write (WE Controlled) L H DIN ACTIVE Byte Write (CE Controlled) L H DIN ACTIVE Standby and Write Inhibit H X X High−Z STANDBY Read and Write Inhibit X H H High−Z ACTIVE |
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