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CAT24WC66WI-1.8-GT3C Fiches technique(PDF) 7 Page - ON Semiconductor

No de pièce CAT24WC66WI-1.8-GT3C
Description  64-Kb I2C Serial EEPROM with Partial Array Write Protection
Download  11 Pages
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT24WC66WI-1.8-GT3C Fiches technique(HTML) 7 Page - ON Semiconductor

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CAT24WC66
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address N+1. If N=E (where E=8191), then the counter will
‘wrap around’ to address 0 and continue to clock out data.
After the CAT24WC66 receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8 bit byte requested. The
master device does not send an acknowledge, but will
generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After CAT24WC66 acknowledges, the Master device sends
the START condition and the slave address again, this time
with the R/W bit set to one. The CAT24WC66 then responds
with its acknowledge and sends the 8−bit byte requested.
The master device does not send an acknowledge but will
generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT24WC66 sends the initial 8−bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more data.
The CAT24WC66 will continue to output an 8−bit byte for
each acknowledge sent by the Master. The operation will
terminate when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24WC66 is
outputted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24WC66 address bits so
that the entire memory array can be read during one
operation. If more than E (where E=8191) bytes are read out,
the counter will ‘wrap around’ and continue to clock out data
bytes.
Figure 9. Immediate Address Read Timing
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
89
SLAVE
ADDRESS
S
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
N
O
A
C
K
DATA
S
T
O
P
P
Figure 10. Selective Read Timing
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE ADDRESS
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
A
R
T
DATA
P
S
T
O
P
XX
X
A15−A8
A7−A0
Figure 11. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
A
C
K
P
SLAVE
ADDRESS
DATA n+2
DATA n+x


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