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TL16C752C Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce TL16C752C
Description  DUAL UART WITH 64-BYTE FIFO
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

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TL16C752C
www.ti.com .................................................................................................................................................... SLLS646A – MARCH 2008 – REVISED AUGUST 2009
Hardware Flow Control
Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be
enabled/disabled independently by programming EFR[7:6].
With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output
when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is
sufficiently full. The HALT and RESTORE trigger levels in the TCR determine the levels at which RTS is
activated/deactivated. If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated
during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive
FIFO servicing latency.
Auto-RTS
Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS
functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the
RX FIFO level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is
reached, RTS is deasserted. The sending device (e.g., another UART) may send an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the
deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.
A.
N = receiver FIFO trigger level B.
B.
The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.
Figure 1. RTS Functional Timing
Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter
sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the
middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error can result. Figure 2 shows CTS functional timing, and Figure 3 shows
an example of autoflow control.
Copyright © 2008–2009, Texas Instruments Incorporated
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