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74LVT16374ADGG Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74LVT16374ADGG Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 19 page 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 10 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Enable and disable times 001aae464 tPZL nYn output nYn output nOE input VOL VOH 3.0 V VI VM GND 0 V tPLZ tPZH tPHZ VX VY VM VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times 001aaa257 GND GND th tsu th tsu VM VM VM VI VOH VOL VI nQn output nCP input nDn input |
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