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74LVC2G74DP Fiches technique(PDF) 9 Page - NXP Semiconductors |
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74LVC2G74DP Fiches technique(HTML) 9 Page - NXP Semiconductors |
9 / 21 page 74LVC2G74_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 23 December 2009 9 of 21 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger [1] Typical values are measured at Tamb =25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. trec recovery time SD or RD; see Figure 9 VCC = 1.65 V to 1.95 V 1.9 - - 1.9 - ns VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - ns VCC = 2.7 V 1.3 - - 1.3 - ns VCC = 3.0 V to 3.6 V +1.2 −3.0 - +1.2 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns tsu set-up time D to CP; see Figure 8 VCC = 1.65 V to 1.95 V 2.9 - - 2.9 - ns VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - ns VCC = 2.7 V 1.7 - - 1.7 - ns VCC = 3.0 V to 3.6 V 1.3 0.5 - 1.3 - ns VCC = 4.5 V to 5.5 V 1.1 - - 1.1 - ns th hold time D to CP; see Figure 8 VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 1.0 - - 1.0 - ns VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V 1.0 0.6 - 1.0 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns fmax maximum frequency CP; see Figure 8 VCC = 1.65 V to 1.95 V 80 - - 80 - MHz VCC = 2.3 V to 2.7 V 175 - - 175 - MHz VCC = 2.7 V 175 - - 175 - MHz VCC = 3.0 V to 3.6 V 175 280 - 175 - MHz VCC = 4.5 V to 5.5 V 200 - - 200 - MHz CPD power dissipation capacitance VI = GND to VCC; VCC = 3.3 V [3] -15- - - pF Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max |
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