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74LVC2G00GM Fiches technique(PDF) 4 Page - NXP Semiconductors

No de pièce 74LVC2G00GM
Description  Dual 2-input NAND gate
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVC2G00GM Fiches technique(HTML) 4 Page - NXP Semiconductors

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74LVC2G00_8
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 26 October 2009
4 of 16
NXP Semiconductors
74LVC2G00
Dual 2-input NAND gate
7.
Functional description
[1]
H = HIGH voltage level; L = LOW voltage level.
8.
Limiting values
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP8 package: above 55
°C the value of P
tot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110
°C the value of P
tot derates linearly with 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C the value of P
tot derates linearly with 2.4 mW/K.
Table 4.
Function table[1]
Input
Output
nA
nB
nY
LLH
LH
H
HL
H
HHL
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+6.5
V
VI
input voltage
[1]
−0.5
+6.5
V
VO
output voltage
Active mode
[1]
−0.5
VCC + 0.5
V
Power-down mode
[1][2]
−0.5
+6.5
V
IIK
input clamping current
VI <0V
−50
-
mA
IOK
output clamping current
VO < 0 V or VO >VCC
-
±50
mA
IO
output current
VO =0Vto VCC
-
±50
mA
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
[3] -
300
mW


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