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74HC2G32GD Fiches technique(PDF) 6 Page - NXP Semiconductors |
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74HC2G32GD Fiches technique(HTML) 6 Page - NXP Semiconductors |
6 / 13 page 74HC_HCT2G32_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 12 May 2009 6 of 13 NXP Semiconductors 74HC2G32; 74HCT2G32 Dual 2-input OR gate [1] tpd is the same as tPLH and tPHL. [2] tt is the same as tTLH and tTHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of the outputs. 12. Waveforms 74HCT2G32 tpd propagation delay nA, nB to nY; see Figure 6 [1] VCC = 4.5 V - 13 24 - 30 - 36 ns tt transition time nY; see Figure 6 [2] VCC = 4.5 V - 6 15 - 19 - 22 ns CPD power dissipation capacitance per buffer; CL = 50 pF; fi = 1 MHz; VI = GND to VCC [3] -11- - - - - pF Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY) 001aak020 nA, nB input nY output tTHL tTLH VM VI GND VOH VOL VM VX VY tPHL tPLH Table 9. Measurement points Type Input Output VM VM VX VY 74HC2G32 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT2G32 1.3 V 1.3 V 0.1VCC 0.9VCC |
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